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Renesas Electronics /R7FA6T3BB /I3C /SCSTLCTL

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Interpret as SCSTLCTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STLCYC0 (0)AAPE 0 (0)PARPE 0 (0)ACKPE

PARPE=0, AAPE=0, ACKPE=0

Description

SCL Stalling Control Register

Fields

STLCYC

Stalling Cycle
AAPE

Assigned Address Phase Enable

0 (0): Does not stall the SCL clock during the address assignment phase.

1 (1): Stall the SCL clock during address assignment phase.
PARPE

Parity Phase Enable

0 (0): Does not stall the SCL clock during the parity bit period.

1 (1): Stall the SCL clock during the parity bit period.
ACKPE

ACK phase Enable

0 (0): Does not stall the SCL clock during the ACK/NACK phase.

1 (1): Stall the SCL clock during the ACK/NACK phase.

Links

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Register License

This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all applicable laws, including copyright laws.

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Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of this software. By using this software, you agree to the additional terms and conditions found by accessing the following link: http://www.renesas.com/disclaimer

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data